Parallel Huffman Decoder with an Optimize Look UP

Total Bit = PnXBi t Abstract Compression is very important for system with limited channel bandwidth and/or limited storage size. One of the main components in imagehideo compression is a variable length coding (VLC). This paper would discuss about one of the most popular VLC known as Huffman Coding. In our present work, a real time hardware parallel Huffman decoder has been successfully designed and implemented using 50,000 gate FPGA (FLEX1OK20 from Altera). The parallelism is important to be exploited in the design to achieve the high frame rate such as in JPEG and MPEG implementation. Using parallel technique, a codeword is guaranteed to be processed within a single clock cycle. The codeword to be processed is matched with the one stored in a Look Up Table (LUT). A LUT is needed during Coder and Decoder process. In order to saves memory cost, an optimize LUT is suggested. This paper does not intend to complete an optimized operating speed design, instead this paper only concentrate on producing a workable real-time decoder design.